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Buffers and Line Drivers 74AUP1G34FW4-7
Diodes Incorporated
74AUP1G34FW4-7
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Standard and Specialty Logic
Buffers and Line Drivers
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Surface Mount |
| Polarity | Non-Inverting |
| ECCN (US) | EAR99 |
| Pin Count | 6 |
| Automotive | No |
| Lead Shape | No Lead |
| PCB changed | 6 |
| Part Status | Active |
| Logic Family | AUP |
| Package Width | 1 |
| Logic Function | Buffer |
| Package Height | 0.37 |
| Package Length | 1 |
| Supplier Package | X2-DFN |
| Input Signal Type | Single-Ended |
| Process Technology | CMOS |
| Standard Package Name | DFN |
| Number of Inputs per Chip | 1 |
| Number of Outputs per Chip | 1 |
| Number of Channels per Chip | 1 |
| Number of Elements per Chip | 1 |
| Maximum Quiescent Current (uA) | 0.5 |
| Number of Input Enables per Chip | 0 |
| Number of Output Enables per Chip | 0 |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -40 |
| Absolute Propagation Delay Time (ns) | 20.8 |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Minimum Operating Supply Voltage (V) | 0.8 |
| Typical Operating Supply Voltage (V) | 3.3|2.5|1.8 |
| Maximum Low Level Output Current (mA) | 4 |
| Propagation Delay Test Condition (pF) | 30 |
| Maximum High Level Output Current (mA) | -4 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 5.6@3V to 3.6V|6.4@2.3V to 2.7V|8.1@1.65V to 1.95V|10.3@1.4V to 1.6V|16.3@1.1V to 1.3V |
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