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Counter Shift Registers 74F269SC
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74F269SC
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Standard and Specialty Logic
Counter Shift Registers
Specification
| Product Attribute | Attribute Value |
| HTS | 8542330001 |
| PPAP | No |
| Type | Binary |
| EU RoHS | Compliant |
| Mounting | Surface Mount |
| ECCN (US) | EAR99 |
| Packaging | Rail |
| Pin Count | 24 |
| Automotive | No |
| Lead Shape | Gull-wing |
| PCB changed | 24 |
| Part Status | Obsolete |
| Preset Type | Synchronous |
| Logic Family | F |
| Package Width | 7.5 |
| Direction Type | Bi-Directional |
| Logic Function | Counter |
| Operation Mode | UP Counter|Down Counter |
| Package Height | 2.35(Max) |
| Package Length | 15.4 |
| Triggering Type | Positive-Edge |
| Number of Stages | 8 |
| Supplier Package | SOIC W |
| Process Technology | Bipolar |
| Parallel Enable Input | Yes |
| Standard Package Name | SOP |
| Terminal Count Output | Yes |
| Number of Element Inputs | 8 |
| Number of Element Outputs | 8 |
| Number of Elements per Chip | 1 |
| Number of Count Input Enables | 2 |
| Maximum Operating Temperature (°C) | 70 |
| Minimum Operating Temperature (°C) | 0 |
| Absolute Propagation Delay Time (ns) | 11.5 |
| Maximum Operating Supply Voltage (V) | 5.5 |
| Minimum Operating Supply Voltage (V) | 4.5 |
| Typical Operating Supply Voltage (V) | 5 |
| Propagation Delay Test Condition (pF) | 50 |
| Number of Selection Inputs per Element | 0 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 10.5@5V |
| Description |
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