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Counter Shift Registers 74LVC169D,112
NXP
74LVC169D,112
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Standard and Specialty Logic
Counter Shift Registers
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| Type | Binary |
| EU RoHS | Supplier Unconfirmed |
| Mounting | Surface Mount |
| ECCN (US) | EAR99 |
| Packaging | Bulk |
| Pin Count | 16 |
| Automotive | No |
| PCB changed | 16 |
| Part Status | Obsolete |
| Preset Type | Synchronous |
| Logic Family | LVC |
| Package Width | 4(Max) |
| Direction Type | Bi-Directional |
| Logic Function | Counter |
| Operation Mode | UP Counter|Down Counter |
| Package Height | 1.45(Max) |
| Package Length | 10(Max) |
| Triggering Type | Positive-Edge |
| Number of Stages | 4 |
| Supplier Package | SO |
| Process Technology | CMOS |
| Parallel Enable Input | Yes |
| Terminal Count Output | Yes |
| Number of Element Inputs | 4 |
| Number of Element Outputs | 4 |
| Number of Elements per Chip | 1 |
| Number of Count Input Enables | 2 |
| Maximum Quiescent Current (mA) | 0.0001(Typ) |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -40 |
| Absolute Propagation Delay Time (ns) | 17.2 |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Minimum Operating Supply Voltage (V) | 1.2 |
| Typical Operating Supply Voltage (V) | 3.3|2.5|1.8 |
| Propagation Delay Test Condition (pF) | 50 |
| Number of Selection Inputs per Element | 0 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 3.9(Typ)@2.7V|3.7(Typ)@3.3V |
| Description |
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