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Counter Shift Registers CD4021BCM
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CD4021BCM
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Standard and Specialty Logic
Counter Shift Registers
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| EU RoHS | Compliant |
| Mounting | Surface Mount |
| ECCN (US) | EAR99 |
| Packaging | Rail |
| Pin Count | 16 |
| Automotive | No |
| Lead Shape | Gull-wing |
| PCB changed | 16 |
| Part Status | Obsolete |
| Logic Family | CD4000 |
| Package Width | 4(Max) |
| Direction Type | Uni-Directional |
| Logic Function | Shift Register |
| Operation Mode | Serial/Parallel to Parallel |
| Package Height | 1.5(Max) |
| Package Length | 10(Max) |
| Triggering Type | Positive-Edge |
| Number of Stages | 8 |
| Supplier Package | SOIC N |
| Process Technology | CMOS |
| Parallel Enable Input | Yes |
| Standard Package Name | SOP |
| Terminal Count Output | No |
| Number of Element Inputs | 9 |
| Number of Element Outputs | 3 |
| Number of Elements per Chip | 1 |
| Number of Count Input Enables | 0 |
| Maximum Quiescent Current (mA) | 0.02 |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -55 |
| Absolute Propagation Delay Time (ns) | 350 |
| Maximum Operating Supply Voltage (V) | 15 |
| Minimum Operating Supply Voltage (V) | 3 |
| Typical Operating Supply Voltage (V) | 12|3.3|5|9 |
| Propagation Delay Test Condition (pF) | 50 |
| Number of Selection Inputs per Element | 0 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 175@10V|350@5V|140@15V |
| Description |
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