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Counter Shift Registers CD4024BCN
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CD4024BCN
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Standard and Specialty Logic
Counter Shift Registers
Specification
| Product Attribute | Attribute Value |
| HTS | 8542330001 |
| PPAP | No |
| Type | Binary |
| EU RoHS | Compliant |
| Mounting | Through Hole |
| ECCN (US) | EAR99 |
| Packaging | Rail |
| Pin Count | 14 |
| Automotive | No |
| Lead Shape | Through Hole |
| PCB changed | 14 |
| Part Status | Obsolete |
| Logic Family | CD4000 |
| Package Width | 6.6(Max) |
| Direction Type | Uni-Directional |
| Logic Function | Counter/Divider |
| Operation Mode | UP Counter |
| Package Height | 3.56(Max) |
| Package Length | 19.56(Max) |
| Triggering Type | Negative-Edge |
| Number of Stages | 7 |
| Supplier Package | PDIP |
| Process Technology | CMOS |
| Parallel Enable Input | No |
| Standard Package Name | DIP |
| Terminal Count Output | No |
| Number of Element Inputs | 1 |
| Number of Element Outputs | 7 |
| Number of Elements per Chip | 1 |
| Number of Count Input Enables | 0 |
| Maximum Quiescent Current (mA) | 0.02 |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -55 |
| Absolute Propagation Delay Time (ns) | 350 |
| Maximum Operating Supply Voltage (V) | 15 |
| Minimum Operating Supply Voltage (V) | 3 |
| Typical Operating Supply Voltage (V) | 3.3|5|9|12 |
| Propagation Delay Test Condition (pF) | 50 |
| Number of Selection Inputs per Element | 0 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 350@5V|125@10V|100@15V |
| Description |
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