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Counter Shift Registers NLV14060BDG
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NLV14060BDG
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Standard and Specialty Logic
Counter Shift Registers
Specification
| Product Attribute | Attribute Value |
| HTS | 8542.39.00.01 |
| PPAP | Yes |
| Type | Binary |
| EU RoHS | Compliant |
| Mounting | Surface Mount |
| ECCN (US) | EAR99 |
| Packaging | Tube |
| Pin Count | 16 |
| Automotive | Yes |
| Lead Shape | Gull-wing |
| PCB changed | 16 |
| Part Status | Obsolete |
| Logic Family | 4000 |
| Package Width | 4(Max) |
| Direction Type | Uni-Directional |
| Logic Function | Counter/Divider |
| Operation Mode | UP Counter |
| Package Height | 1.5(Max) |
| Package Length | 10(Max) |
| Triggering Type | Negative-Edge |
| Number of Stages | 14 |
| Supplier Package | SOIC |
| Process Technology | CMOS |
| Parallel Enable Input | No |
| Standard Package Name | SOP |
| Terminal Count Output | No |
| Number of Element Inputs | 1 |
| Number of Element Outputs | 10 |
| Number of Elements per Chip | 1 |
| Number of Count Input Enables | 0 |
| Maximum Quiescent Current (mA) | 0.02 |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -55 |
| Absolute Propagation Delay Time (ns) | 2700 |
| Maximum Operating Supply Voltage (V) | 18 |
| Minimum Operating Supply Voltage (V) | 3 |
| Typical Operating Supply Voltage (V) | 3.3|5|9|12|15 |
| Propagation Delay Test Condition (pF) | 50 |
| Number of Selection Inputs per Element | 0 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 2700@5V|1300@10V|1000@15V |
| Description |
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