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DRAM Chip K4T1G084QJ-BCE7TCV
Samsung Electronics
K4T1G084QJ-BCE7TCV
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Memory
DRAM Chip
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| EU RoHS | Compliant |
| Mounting | Surface Mount |
| DRAM Type | DDR2 SDRAM |
| ECCN (US) | EAR99 |
| Pin Count | 60 |
| Automotive | No |
| Lead Shape | Ball |
| PCB changed | 60 |
| Part Status | Obsolete |
| Organization | 128Mx8 |
| Package Width | 7.5 |
| Interface Type | SSTL_1.8 |
| Package Height | 0.53 + 0.1(Max) |
| Package Length | 9.5 |
| Supplier Package | FBGA |
| Chip Density (bit) | 1G |
| Data Bus Width (bit) | 8 |
| Standard Package Name | BGA |
| Operating Current (mA) | 65 |
| Address Bus Width (bit) | 17 |
| Maximum Access Time (ns) | 0.4 |
| Maximum Clock Rate (MHz) | 800 |
| Number of Internal Banks | 8 |
| Number of Words per Bank | 16M |
| Number of Bits/Word (bit) | 8 |
| Number of I/O Lines (bit) | 8 |
| Supplier Temperature Grade | Commercial |
| Maximum Operating Temperature (°C) | 95 |
| Minimum Operating Temperature (°C) | 0 |
| Maximum Operating Supply Voltage (V) | 1.9 |
| Minimum Operating Supply Voltage (V) | 1.7 |
| Typical Operating Supply Voltage (V) | 1.8 |
| Description |
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