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DRAM Chip MT48LC2M32B2TG-55:G
Micron Technology
MT48LC2M32B2TG-55:G
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Memory
DRAM Chip
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| EU RoHS | Not Compliant |
| Mounting | Surface Mount |
| DRAM Type | SDR SDRAM |
| ECCN (US) | EAR99 |
| Packaging | Tray |
| Pin Count | 86 |
| Automotive | No |
| Lead Shape | Gull-wing |
| PCB changed | 86 |
| Part Status | Obsolete |
| Organization | 2Mx32 |
| Package Width | 10.16 |
| Interface Type | LVTTL |
| Package Height | 1(Max) |
| Package Length | 22.22 |
| Supplier Package | TSOP-II |
| Chip Density (bit) | 64M |
| Process Technology | CMOS |
| Data Bus Width (bit) | 32 |
| Standard Package Name | SOP |
| Operating Current (mA) | 260 |
| Address Bus Width (bit) | 13 |
| Maximum Access Time (ns) | 5 |
| Maximum Clock Rate (MHz) | 183 |
| Number of Internal Banks | 4 |
| Number of Words per Bank | 512K |
| Number of Bits/Word (bit) | 32 |
| Number of I/O Lines (bit) | 32 |
| Supplier Temperature Grade | Commercial |
| Maximum Operating Temperature (°C) | 70 |
| Minimum Operating Temperature (°C) | 0 |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Minimum Operating Supply Voltage (V) | 3 |
| Typical Operating Supply Voltage (V) | 3.3 |
| Description |
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