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Flip Flops 74AUP2G79GN,115
Nexperia
74AUP2G79GN,115
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Standard and Specialty Logic
Flip Flops
Specification
| Product Attribute | Attribute Value |
| PPAP | Unknown |
| SVHC | Yes |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Surface Mount |
| Polarity | Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Tape and Reel |
| Pin Count | 8 |
| Automotive | Unknown |
| PCB changed | 8 |
| Part Status | Active |
| Logic Family | AUP |
| Package Width | 1 |
| Logic Function | D-Type |
| Package Height | 0.31(Max) |
| Package Length | 1.2 |
| Triggering Type | Positive-Edge |
| Supplier Package | XSON |
| Input Signal Type | Single-Ended |
| Process Technology | CMOS |
| Number of Element Inputs | 1 |
| Number of Element Outputs | 1 |
| Number of Channels per Chip | 2 |
| Number of Elements per Chip | 2 |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -40 |
| Absolute Propagation Delay Time (ns) | 25.6 |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Minimum Operating Supply Voltage (V) | 0.8 |
| Typical Operating Supply Voltage (V) | 3.3|2.5|1.8 |
| Maximum Low Level Output Current (mA) | 4 |
| Propagation Delay Test Condition (pF) | 30 |
| Maximum High Level Output Current (mA) | -4 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 5.8@3V to 3.6V|7@2.3V to 2.7V|9.4@1.65V to 1.95V|11.8@1.4V to 1.6V|17.3@1.1V to 1.3V |
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