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74F112PC
74F112PC
Flip Flops 74F112PC
onsemi
74F112PC
--
Standard and Specialty Logic
Flip Flops
74F112PC.pdf
Specification
Product AttributeAttribute Value
HTS8542.31.00.01
PPAPNo
EU RoHSCompliant
Bus HoldNo
MountingThrough Hole
PolarityInverting/Non-Inverting
ECCN (US)EAR99
PackagingRail
Pin Count16
Set/ResetSet/Reset
AutomotiveNo
Lead ShapeThrough Hole
PCB changed16
Part StatusObsolete
Logic FamilyF
Package Width7.11(Max)
Logic FunctionJK-Type
Package Height4.95(Max)
Package Length19.69(Max)
Triggering TypeNegative-Edge
Supplier PackagePDIP
Input Signal TypeSingle-Ended
Process TechnologyBipolar
Standard Package NameDIP
Number of Element Inputs2
Number of Element Outputs1
Number of Channels per Chip2
Number of Elements per Chip2
Maximum Operating Temperature (°C)70
Minimum Operating Temperature (°C)0
Absolute Propagation Delay Time (ns)7.5
Maximum Operating Supply Voltage (V)5.5
Minimum Operating Supply Voltage (V)4.5
Typical Operating Supply Voltage (V)5
Maximum Low Level Output Current (mA)20
Propagation Delay Test Condition (pF)50
Maximum High Level Output Current (mA)-1
Maximum Propagation Delay Time @ Maximum CL (ns)6.5@5V
Description
Flip Flop JK-Type Neg-Edge 2-Element 16-Pin PDIP Rail
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