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Flip Flops 74HC112PW,118
Nexperia
74HC112PW,118
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Standard and Specialty Logic
Flip Flops
Specification
| Product Attribute | Attribute Value |
| HTS | 8542330001 |
| PPAP | No |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Surface Mount |
| Polarity | Inverting/Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Tape and Reel |
| Pin Count | 16 |
| Set/Reset | Set/Reset |
| Automotive | No |
| PCB changed | 16 |
| Part Status | Active |
| Logic Family | HC |
| Package Width | 4.5(Max) |
| Logic Function | JK-Type |
| Package Height | 0.95(Max) |
| Package Length | 5.1(Max) |
| Triggering Type | Negative-Edge |
| Supplier Package | TSSOP |
| Input Signal Type | Single-Ended |
| Process Technology | CMOS |
| Standard Package Name | SOP |
| Number of Element Inputs | 2 |
| Number of Element Outputs | 1 |
| Number of Channels per Chip | 2 |
| Number of Elements per Chip | 2 |
| Maximum Quiescent Current (mA) | 0.004 |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -40 |
| Absolute Propagation Delay Time (ns) | 270 |
| Maximum Operating Supply Voltage (V) | 6 |
| Minimum Operating Supply Voltage (V) | 2 |
| Typical Operating Supply Voltage (V) | 5 |
| Maximum Low Level Output Current (mA) | 7.8 |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -7.8 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 175@2V|35@4.5V|30@6V |
| Description |
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