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Flip Flops 74LVCH16374ADGG:51
NXP
74LVCH16374ADGG:51
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Standard and Specialty Logic
Flip Flops
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| EU RoHS | Compliant |
| Bus Hold | Yes |
| Mounting | Surface Mount |
| Polarity | Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Tube |
| Pin Count | 48 |
| Automotive | No |
| Output Type | 3-State |
| PCB changed | 48 |
| Part Status | Obsolete |
| Logic Family | LVC |
| Package Width | 6.2(Max) |
| Logic Function | D-Type Bus Interface |
| Package Height | 1.05(Max) |
| Package Length | 12.6(Max) |
| Triggering Type | Positive-Edge |
| Supplier Package | TSSOP |
| Input Signal Type | Single-Ended |
| Process Technology | CMOS |
| Number of Element Inputs | 8 |
| Number of Element Outputs | 8 |
| Number of Channels per Chip | 16 |
| Number of Elements per Chip | 2 |
| Maximum Quiescent Current (mA) | 0.0001(Typ) |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -40 |
| Absolute Propagation Delay Time (ns) | 7.5 |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Minimum Operating Supply Voltage (V) | 1.2 |
| Number of Output Enables per Element | 1 |
| Typical Operating Supply Voltage (V) | 1.8|2.5|3.3 |
| Maximum Low Level Output Current (mA) | 24 |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -24 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 14(Typ)@1.2V|3.4(Typ)@3.3V |
| Description |
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