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Flip Flops 74LVT374DB,112
NXP
74LVT374DB,112
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Standard and Specialty Logic
Flip Flops
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| EU RoHS | Supplier Unconfirmed |
| Bus Hold | Yes |
| Mounting | Surface Mount |
| Polarity | Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Bulk |
| Pin Count | 20 |
| Automotive | No |
| Output Type | 3-State |
| PCB changed | 20 |
| Part Status | Obsolete |
| Logic Family | LVT |
| Package Width | 5.4(Max) |
| Logic Function | D-Type Bus Interface |
| Package Height | 1.8(Max) |
| Package Length | 7.4(Max) |
| Triggering Type | Positive-Edge |
| Supplier Package | SSOP |
| Input Signal Type | Single-Ended |
| Process Technology | BiCMOS |
| Number of Element Inputs | 8 |
| Number of Element Outputs | 8 |
| Number of Channels per Chip | 8 |
| Number of Elements per Chip | 1 |
| Maximum Quiescent Current (mA) | 3(Typ) |
| Maximum Operating Temperature (°C) | 85 |
| Minimum Operating Temperature (°C) | -40 |
| Absolute Propagation Delay Time (ns) | 7.3 |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Minimum Operating Supply Voltage (V) | 2.7 |
| Number of Output Enables per Element | 1 |
| Typical Operating Supply Voltage (V) | 3.3 |
| Maximum Low Level Output Current (mA) | 64 |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -32 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 3.5(Typ)@3.3V |
| Description |
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