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CD4027BNSRG4
CD4027BNSRG4
Flip Flops CD4027BNSRG4
Texas Instruments
CD4027BNSRG4
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Standard and Specialty Logic
Flip Flops
Specification
Product AttributeAttribute Value
PPAPNo
EU RoHSCompliant
Bus HoldNo
MountingSurface Mount
PolarityInverting/Non-Inverting
ECCN (US)EAR99
PackagingTape and Reel
Pin Count16
Set/ResetSet/Reset
AutomotiveNo
Lead ShapeGull-wing
PCB changed16
Part StatusActive
Logic FamilyCD4000
Package Width5.6(Max)
Logic FunctionJK-Master-Slave Type
Package Height1.85(Max)
Package Length10.5(Max)
Triggering TypePositive-Edge
Supplier PackageSOP
Input Signal TypeSingle-Ended
Process TechnologyCMOS
Standard Package NameSOP
Number of Element Inputs2
Number of Element Outputs1
Supplier Temperature GradeMilitary
Number of Channels per Chip2
Number of Elements per Chip2
Maximum Quiescent Current (mA)0.02
Maximum Operating Temperature (°C)125
Minimum Operating Temperature (°C)-55
Absolute Propagation Delay Time (ns)400
Maximum Operating Supply Voltage (V)18
Minimum Operating Supply Voltage (V)3
Typical Operating Supply Voltage (V)15|3.3|5|9|12
Maximum Low Level Output Current (mA)4.2(Min)
Propagation Delay Test Condition (pF)50
Maximum High Level Output Current (mA)-4.2(Min)
Maximum Propagation Delay Time @ Maximum CL (ns)300@5V|130@10V|90@15V
Description
Flip Flop JK-Master-Slave Type Pos-Edge 2-Element 16-Pin SOP T/R
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