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CD74HC112EE4
CD74HC112EE4
Flip Flops CD74HC112EE4
Texas Instruments
CD74HC112EE4
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Standard and Specialty Logic
Flip Flops
Specification
Product AttributeAttribute Value
PPAPNo
SVHCYes
EU RoHSCompliant
Bus HoldNo
MountingThrough Hole
PolarityInverting/Non-Inverting
ECCN (US)EAR99
PackagingTube
Pin Count16
Set/ResetSet/Reset
AutomotiveNo
Lead ShapeThrough Hole
PCB changed16
Part StatusObsolete
Logic FamilyHC
Package Width6.6(Max)
Logic FunctionJK-Type
Package Height5.08(Max) - 0.51(Min)
Package Length19.69(Max)
Triggering TypeNegative-Edge
Supplier PackagePDIP
Input Signal TypeSingle-Ended
Process TechnologyCMOS
Standard Package NameDIP
Number of Element Inputs2
Number of Element Outputs1
Number of Channels per Chip2
Number of Elements per Chip2
Maximum Quiescent Current (mA)0.004
Maximum Operating Temperature (°C)125
Minimum Operating Temperature (°C)-55
Absolute Propagation Delay Time (ns)270
Maximum Operating Supply Voltage (V)6
Minimum Operating Supply Voltage (V)2
Typical Operating Supply Voltage (V)2.5|3.3|5
Maximum Low Level Output Current (mA)5.2
Propagation Delay Test Condition (pF)50
Maximum High Level Output Current (mA)-5.2
Maximum Propagation Delay Time @ Maximum CL (ns)30@6V|175@2V|35@4.5V
Description
Flip Flop JK-Type Neg-Edge 2-Element 16-Pin PDIP Tube
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