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Flip Flops CD74HC112EE4
Texas Instruments
CD74HC112EE4
--
Standard and Specialty Logic
Flip Flops
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| SVHC | Yes |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Through Hole |
| Polarity | Inverting/Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Tube |
| Pin Count | 16 |
| Set/Reset | Set/Reset |
| Automotive | No |
| Lead Shape | Through Hole |
| PCB changed | 16 |
| Part Status | Obsolete |
| Logic Family | HC |
| Package Width | 6.6(Max) |
| Logic Function | JK-Type |
| Package Height | 5.08(Max) - 0.51(Min) |
| Package Length | 19.69(Max) |
| Triggering Type | Negative-Edge |
| Supplier Package | PDIP |
| Input Signal Type | Single-Ended |
| Process Technology | CMOS |
| Standard Package Name | DIP |
| Number of Element Inputs | 2 |
| Number of Element Outputs | 1 |
| Number of Channels per Chip | 2 |
| Number of Elements per Chip | 2 |
| Maximum Quiescent Current (mA) | 0.004 |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -55 |
| Absolute Propagation Delay Time (ns) | 270 |
| Maximum Operating Supply Voltage (V) | 6 |
| Minimum Operating Supply Voltage (V) | 2 |
| Typical Operating Supply Voltage (V) | 2.5|3.3|5 |
| Maximum Low Level Output Current (mA) | 5.2 |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -5.2 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 30@6V|175@2V|35@4.5V |
| Description |
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