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Flip Flops HEF40174BP,652
NXP
HEF40174BP,652
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Standard and Specialty Logic
Flip Flops
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| EU RoHS | Supplier Unconfirmed |
| Bus Hold | No |
| Mounting | Through Hole |
| Polarity | Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Bulk |
| Pin Count | 16 |
| Set/Reset | Master Reset |
| Automotive | No |
| PCB changed | 16 |
| Part Status | Obsolete |
| Logic Family | HEF4000 |
| Package Width | 6.48(Max) |
| Logic Function | D-Type Bus Interface |
| Package Height | 3.2(Max) |
| Package Length | 19.5(Max) |
| Triggering Type | Positive-Edge |
| Supplier Package | PDIP |
| Input Signal Type | Single-Ended |
| Process Technology | CMOS |
| Number of Element Inputs | 6 |
| Number of Element Outputs | 6 |
| Supplier Temperature Grade | Industrial |
| Number of Channels per Chip | 6 |
| Number of Elements per Chip | 1 |
| Maximum Quiescent Current (mA) | 0.08 |
| Maximum Operating Temperature (°C) | 85 |
| Minimum Operating Temperature (°C) | -40 |
| Absolute Propagation Delay Time (ns) | 175 |
| Maximum Operating Supply Voltage (V) | 15 |
| Minimum Operating Supply Voltage (V) | 3 |
| Typical Operating Supply Voltage (V) | 9|12|5|3.3 |
| Maximum Low Level Output Current (mA) | 3.6(Min) |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -3.6(Min) |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 155@5V|65@10V|45@15V |
| Description |
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