Product Attribute | Attribute Value |
PPAP | No |
SVHC | Yes |
EU RoHS | Not Compliant |
Bus Hold | No |
Mounting | Through Hole |
Polarity | Inverting/Non-Inverting |
ECCN (US) | EAR99 |
Packaging | Tube |
Pin Count | 16 |
Set/Reset | Set/Reset |
Automotive | No |
Lead Shape | Through Hole |
PCB changed | 16 |
Part Status | Active |
Logic Family | CD4000 |
Package Width | 7.62(Max) |
Logic Function | JK-Master-Slave Type |
Package Height | 3.56(Max) |
Package Length | 21.34(Max) |
Triggering Type | Positive-Edge |
Supplier Package | CDIP |
Input Signal Type | Single-Ended |
Process Technology | CMOS |
Standard Package Name | DIP |
Number of Element Inputs | 2 |
Number of Element Outputs | 1 |
Supplier Temperature Grade | Military |
Number of Channels per Chip | 2 |
Number of Elements per Chip | 2 |
Maximum Quiescent Current (mA) | 0.02 |
Maximum Operating Temperature (°C) | 125 |
Minimum Operating Temperature (°C) | -55 |
Absolute Propagation Delay Time (ns) | 400 |
Maximum Operating Supply Voltage (V) | 18 |
Minimum Operating Supply Voltage (V) | 3 |
Typical Operating Supply Voltage (V) | 3.3|5|9|12|15 |
Maximum Low Level Output Current (mA) | 4.2(Min) |
Propagation Delay Test Condition (pF) | 50 |
Maximum High Level Output Current (mA) | -4.2(Min) |
Maximum Propagation Delay Time @ Maximum CL (ns) | 300@5V|130@10V|90@15V |
Description |