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Flip Flops MC100EL51DR2G
onsemi
MC100EL51DR2G
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Standard and Specialty Logic
Flip Flops
Specification
| Product Attribute | Attribute Value |
| HTS | 8542330001 |
| PPAP | No |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Surface Mount |
| Polarity | Inverting/Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Tape and Reel |
| Pin Count | 8 |
| Set/Reset | Reset |
| Automotive | No |
| Lead Shape | Gull-wing |
| PCB changed | 8 |
| Part Status | Obsolete |
| Logic Family | ECL |
| Package Width | 4(Max) |
| Logic Function | D-Master-Slave Type |
| Package Height | 1.5(Max) |
| Package Length | 5(Max) |
| Triggering Type | Positive-Edge/Negative-Edge |
| Supplier Package | SOIC N |
| Input Signal Type | Single-Ended |
| Process Technology | ECL |
| Standard Package Name | SOP |
| Number of Element Inputs | 1 |
| Number of Element Outputs | 1 |
| Number of Channels per Chip | 1 |
| Number of Elements per Chip | 1 |
| Maximum Operating Temperature (°C) | 85 |
| Minimum Operating Temperature (°C) | -40 |
| Absolute Propagation Delay Time (ns) | 0.62 |
| Maximum Operating Supply Voltage (V) | -5.7|5.7 |
| Minimum Operating Supply Voltage (V) | -4.2|4.2 |
| Typical Operating Supply Voltage (V) | 5|-5 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 0.565@5V |
| Description |
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