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N74F112N,602
N74F112N,602
Flip Flops N74F112N,602
NXP
N74F112N,602
--
Standard and Specialty Logic
Flip Flops
N74F112N,602.pdf
Specification
Product AttributeAttribute Value
PPAPNo
EU RoHSSupplier Unconfirmed
Bus HoldNo
MountingThrough Hole
PolarityInverting/Non-Inverting
ECCN (US)EAR99
PackagingTube
Pin Count16
Set/ResetSet/Reset
AutomotiveNo
PCB changed16
Part StatusObsolete
Logic FamilyF
Package Width6.48(Max)
Logic FunctionJK-Type
Package Height3.2(Max)
Package Length19.5(Max)
Triggering TypeNegative-Edge
Supplier PackagePDIP
Input Signal TypeSingle-Ended
Process TechnologyBipolar
Number of Element Inputs2
Number of Element Outputs1
Supplier Temperature GradeCommercial
Number of Channels per Chip2
Number of Elements per Chip2
Maximum Operating Temperature (°C)70
Minimum Operating Temperature (°C)0
Absolute Propagation Delay Time (ns)7.5
Maximum Operating Supply Voltage (V)5.5
Minimum Operating Supply Voltage (V)4.5
Typical Operating Supply Voltage (V)5
Maximum Low Level Output Current (mA)20
Propagation Delay Test Condition (pF)50
Maximum High Level Output Current (mA)-1
Maximum Propagation Delay Time @ Maximum CL (ns)6.5@5V
Description
Flip Flop JK-Type Neg-Edge 2-Element 16-Pin PDIP Tube
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