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Flip Flops NLV14027BDR2G
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NLV14027BDR2G
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Standard and Specialty Logic
Flip Flops
Specification
| Product Attribute | Attribute Value |
| PPAP | Yes |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Surface Mount |
| Polarity | Inverting/Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Tape and Reel |
| Pin Count | 16 |
| Set/Reset | Set/Reset |
| Automotive | Yes |
| Lead Shape | Gull-wing |
| PCB changed | 16 |
| Part Status | Active |
| Logic Family | 4000 |
| Package Width | 4(Max) |
| Logic Function | JK-Type |
| Package Height | 1.5(Max) |
| Package Length | 10(Max) |
| Triggering Type | Positive-Edge |
| Supplier Package | SOIC |
| Input Signal Type | Single-Ended |
| Process Technology | CMOS |
| Standard Package Name | SOP |
| Number of Element Inputs | 2 |
| Number of Element Outputs | 1 |
| Supplier Temperature Grade | Automotive |
| Number of Channels per Chip | 2 |
| Number of Elements per Chip | 2 |
| Maximum Quiescent Current (mA) | 0.004 |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -55 |
| Absolute Propagation Delay Time (ns) | 450 |
| Maximum Operating Supply Voltage (V) | 18 |
| Minimum Operating Supply Voltage (V) | 3 |
| Typical Operating Supply Voltage (V) | 3.3|5|9|12|15 |
| Maximum Low Level Output Current (mA) | 4.2(Min) |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -4.2(Min) |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 350@5V|150@10V|100@15V |
| Description |
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