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Flip Flops SN74AUC2G80YEPR
Texas Instruments
SN74AUC2G80YEPR
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Standard and Specialty Logic
Flip Flops
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| EU RoHS | Not Compliant |
| Bus Hold | No |
| Mounting | Surface Mount |
| Polarity | Inverting |
| ECCN (US) | EAR99 |
| Packaging | Tape and Reel |
| Pin Count | 8 |
| Automotive | No |
| Lead Shape | Ball |
| PCB changed | 8 |
| Part Status | Obsolete |
| Logic Family | AUC |
| Package Width | 0.9 |
| Logic Function | D-Type |
| Package Height | 0.3 |
| Package Length | 1.9 |
| Triggering Type | Positive-Edge |
| Supplier Package | DSBGA |
| Input Signal Type | Single-Ended |
| Process Technology | CMOS |
| Standard Package Name | BGA |
| Number of Element Inputs | 1 |
| Number of Element Outputs | 1 |
| Supplier Temperature Grade | Commercial |
| Number of Channels per Chip | 2 |
| Number of Elements per Chip | 2 |
| Maximum Quiescent Current (mA) | 0.01 |
| Maximum Operating Temperature (°C) | 85 |
| Minimum Operating Temperature (°C) | -40 |
| Absolute Propagation Delay Time (ns) | 3.9 |
| Maximum Operating Supply Voltage (V) | 2.7 |
| Minimum Operating Supply Voltage (V) | 0.8 |
| Typical Operating Supply Voltage (V) | 1.8|2.5 |
| Maximum Low Level Output Current (mA) | 9 |
| Propagation Delay Test Condition (pF) | 30 |
| Maximum High Level Output Current (mA) | -9 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 2.4@1.8V|1.8@2.5V |
| Description |
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