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Flip Flops SN74F112N
Texas Instruments
SN74F112N
--
Standard and Specialty Logic
Flip Flops
Specification
| Product Attribute | Attribute Value |
| HTS | 8542330001 |
| PPAP | No |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Through Hole |
| Polarity | Inverting/Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Tube |
| Pin Count | 16 |
| Set/Reset | Set/Reset |
| Automotive | No |
| Lead Shape | Through Hole |
| PCB changed | 16 |
| Part Status | Active |
| Logic Family | F |
| Package Width | 6.6(Max) |
| Logic Function | JK-Type |
| Package Height | 5.08(Max) - 0.51(Min) |
| Package Length | 19.69(Max) |
| Triggering Type | Negative-Edge |
| Supplier Package | PDIP |
| Input Signal Type | Single-Ended |
| Process Technology | Bipolar |
| Standard Package Name | DIP |
| Number of Element Inputs | 2 |
| Number of Element Outputs | 1 |
| Number of Channels per Chip | 2 |
| Number of Elements per Chip | 2 |
| Maximum Operating Temperature (°C) | 70 |
| Minimum Operating Temperature (°C) | 0 |
| Absolute Propagation Delay Time (ns) | 7.5 |
| Maximum Operating Supply Voltage (V) | 5.5 |
| Minimum Operating Supply Voltage (V) | 4.5 |
| Typical Operating Supply Voltage (V) | 5 |
| Maximum Low Level Output Current (mA) | 20 |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -1 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 6.5@5V |
| Description |
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