Product Attribute | Attribute Value |
HTS | 8542.39.00.01 |
PPAP | No |
Type | D-Type |
EU RoHS | Not Compliant |
Bus Hold | No |
Mounting | Through Hole |
Polarity | Non-Inverting |
ECCN (US) | 3A001.a.2.c |
Packaging | Rail |
Pin Count | 20 |
Set/Reset | No |
Automotive | No |
Latch Mode | Transparent |
Lead Shape | Through Hole |
Output Type | 3-State |
PCB changed | 20 |
Part Status | Obsolete |
Logic Family | FCT |
Package Width | 7.87(Max) |
Package Height | 4.57(Max) |
Package Length | 25.02(Max) |
Supplier Package | CDIP |
Process Technology | CMOS |
Standard Package Name | DIP |
Number of Inputs per Chip | 8 |
Number of Outputs per Chip | 8 |
Supplier Temperature Grade | Military |
Number of Channels per Chip | 8 |
Number of Elements per Chip | 1 |
Maximum Quiescent Current (uA) | 1500 |
Maximum Operating Temperature (°C) | 125 |
Minimum Operating Temperature (°C) | -55 |
Number of Input Enables per Element | 1 |
Absolute Propagation Delay Time (ns) | 15 |
Maximum Operating Supply Voltage (V) | 5.5 |
Minimum Operating Supply Voltage (V) | 4.5 |
Number of Output Enables per Element | 1 |
Typical Operating Supply Voltage (V) | 5 |
Maximum Low Level Output Current (mA) | 32 |
Propagation Delay Test Condition (pF) | 50 |
Maximum High Level Output Current (mA) | -12 |
Number of Selection Inputs per Element | 0 |
Maximum Propagation Delay Time @ Maximum CL (ns) | 8.5@4.5V to 5.5V |
Description |