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Latches 74ALVT16260DGG,112
NXP
74ALVT16260DGG,112
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Standard and Specialty Logic
Latches
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| Type | D-Type |
| EU RoHS | Compliant |
| Bus Hold | Yes |
| Mounting | Surface Mount |
| Polarity | Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Bulk |
| Pin Count | 56 |
| Set/Reset | No |
| Automotive | No |
| Latch Mode | Multiplexed |
| Output Type | 3-State |
| PCB changed | 56 |
| Part Status | Obsolete |
| Logic Family | ALVT |
| Package Width | 6.2(Max) |
| Package Height | 1.05(Max) |
| Package Length | 14.1(Max) |
| Supplier Package | TSSOP |
| Process Technology | BiCMOS |
| Number of Inputs per Chip | 12 |
| Number of Outputs per Chip | 24 |
| Number of Channels per Chip | 12 |
| Number of Elements per Chip | 1 |
| Maximum Quiescent Current (uA) | 6000 |
| Typical Quiescent Current (uA) | 3700 |
| Maximum Operating Temperature (°C) | 85 |
| Minimum Operating Temperature (°C) | -40 |
| Number of Input Enables per Element | 4 |
| Absolute Propagation Delay Time (ns) | 5.6 |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Minimum Operating Supply Voltage (V) | 2.3 |
| Number of Output Enables per Element | 3 |
| Typical Operating Supply Voltage (V) | 2.5|3.3 |
| Maximum Low Level Output Current (mA) | 64 |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -32 |
| Number of Selection Inputs per Element | 1 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 5.2@2.5V|3.6@3.3V |
| Description |
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