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74LV573N,112
74LV573N,112
Latches 74LV573N,112
NXP
74LV573N,112
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Standard and Specialty Logic
Latches
74LV573N,112.pdf
Specification
Product AttributeAttribute Value
PPAPUnknown
TypeD-Type
EU RoHSSupplier Unconfirmed
Bus HoldNo
MountingThrough Hole
PolarityNon-Inverting
ECCN (US)EAR99
PackagingBulk
Pin Count20
Set/ResetNo
AutomotiveUnknown
Latch ModeTransparent
Output Type3-State
PCB changed20
Part StatusObsolete
Logic FamilyLV
Package Width6.4(Max)
Package Height3.2(Max)
Package Length26.29(Max)
Supplier PackagePDIP
Process TechnologyCMOS
Number of Inputs per Chip8
Number of Outputs per Chip8
Number of Channels per Chip8
Number of Elements per Chip1
Maximum Quiescent Current (uA)160
Maximum Operating Temperature (°C)125
Minimum Operating Temperature (°C)-40
Number of Input Enables per Element1
Absolute Propagation Delay Time (ns)53
Maximum Operating Supply Voltage (V)5.5
Minimum Operating Supply Voltage (V)1
Number of Output Enables per Element1
Typical Operating Supply Voltage (V)3.3
Maximum Low Level Output Current (mA)16
Propagation Delay Test Condition (pF)50
Maximum High Level Output Current (mA)-16
Number of Selection Inputs per Element0
Maximum Propagation Delay Time @ Maximum CL (ns)14(Typ)@3.3V|19(Typ)@2.7V|75(Typ)@1.2V|26(Typ)@2V
Description
Latch Transparent 3-ST 8-CH D-Type Automotive 20-Pin PDIP Bulk
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