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Latches 74LVC16373ADGG,512
NXP
74LVC16373ADGG,512
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Standard and Specialty Logic
Latches
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| Type | D-Type |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Surface Mount |
| Polarity | Non-Inverting |
| ECCN (US) | EAR99 |
| Pin Count | 48 |
| Set/Reset | No |
| Automotive | No |
| Latch Mode | Transparent |
| Output Type | 3-State |
| PCB changed | 48 |
| Part Status | Obsolete |
| Logic Family | LVC |
| Package Width | 6.2(Max) |
| Package Height | 1.05(Max) |
| Package Length | 12.6(Max) |
| Supplier Package | TSSOP |
| Tolerant I/Os (V) | 5 |
| Process Technology | CMOS |
| Number of Inputs per Chip | 16 |
| Number of Outputs per Chip | 16 |
| Number of Channels per Chip | 16 |
| Number of Elements per Chip | 2 |
| Maximum Quiescent Current (uA) | 80 |
| Typical Quiescent Current (uA) | 0.1 |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -40 |
| Number of Input Enables per Element | 1 |
| Absolute Propagation Delay Time (ns) | 14.4 |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Minimum Operating Supply Voltage (V) | 1.2 |
| Number of Output Enables per Element | 1 |
| Typical Operating Supply Voltage (V) | 1.8|2.5|3.3 |
| Maximum Low Level Output Current (mA) | 24 |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -24 |
| Number of Selection Inputs per Element | 0 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 2.9(Typ)@2.7V|2.4(Typ)@3.3V |
| Description |
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