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Latches 74LVC573APW-Q100J
Nexperia
74LVC573APW-Q100J
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Standard and Specialty Logic
Latches
Specification
| Product Attribute | Attribute Value |
| PPAP | Unknown |
| Type | D-Type |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Surface Mount |
| Polarity | Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Tape and Reel |
| Pin Count | 20 |
| Set/Reset | No |
| Automotive | Yes |
| Latch Mode | Transparent |
| Output Type | 3-State |
| PCB changed | 20 |
| Part Status | Active |
| Logic Family | LVC |
| Package Width | 4.5(Max) |
| Package Height | 0.95(Max) |
| Package Length | 6.6(Max) |
| Supplier Package | TSSOP |
| Tolerant I/Os (V) | 5 |
| Process Technology | CMOS |
| Number of Inputs per Chip | 8 |
| Number of Outputs per Chip | 8 |
| Number of Channels per Chip | 8 |
| Number of Elements per Chip | 1 |
| Maximum Quiescent Current (uA) | 40 |
| Typical Quiescent Current (uA) | 0.1 |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -40 |
| Number of Input Enables per Element | 1 |
| Absolute Propagation Delay Time (ns) | 20.2 |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Minimum Operating Supply Voltage (V) | 1.2 |
| Number of Output Enables per Element | 1 |
| Typical Operating Supply Voltage (V) | 3.3|2.5|1.8 |
| Maximum Low Level Output Current (mA) | 24 |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -24 |
| Number of Selection Inputs per Element | 0 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 3.4(Typ)@3V to 3.6V|4.1(Typ)@2.7V |
| Description |
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