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74LVC841APW,118
74LVC841APW,118
Latches 74LVC841APW,118
NXP
74LVC841APW,118
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Standard and Specialty Logic
Latches
Specification
Product AttributeAttribute Value
PPAPNo
TypeD-Type
EU RoHSCompliant
Bus HoldNo
MountingSurface Mount
PolarityNon-Inverting
ECCN (US)EAR99
PackagingTape and Reel
Pin Count24
Set/ResetNo
AutomotiveNo
Latch ModeTransparent
Output Type3-State
PCB changed24
Part StatusObsolete
Logic FamilyLVC
Package Width4.5(Max)
Package Height0.95(Max)
Package Length7.9(Max)
Supplier PackageTSSOP
Tolerant I/Os (V)5
Process TechnologyCMOS
Number of Inputs per Chip10
Number of Outputs per Chip10
Number of Channels per Chip10
Number of Elements per Chip1
Maximum Quiescent Current (uA)40
Typical Quiescent Current (uA)0.1
Maximum Operating Temperature (°C)125
Minimum Operating Temperature (°C)-40
Number of Input Enables per Element1
Absolute Propagation Delay Time (ns)11
Maximum Operating Supply Voltage (V)3.6
Minimum Operating Supply Voltage (V)1.2
Number of Output Enables per Element1
Typical Operating Supply Voltage (V)1.8|2.5|3.3
Maximum Low Level Output Current (mA)24
Propagation Delay Test Condition (pF)50
Maximum High Level Output Current (mA)-24
Number of Selection Inputs per Element0
Maximum Propagation Delay Time @ Maximum CL (ns)15(Typ)@1.2V|3(Typ)@3.3V
Description
Latch Transparent 3-ST 10-CH D-Type 24-Pin TSSOP T/R
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