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Latches HEF4043BT-Q100J
Nexperia
HEF4043BT-Q100J
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Standard and Specialty Logic
Latches
Specification
| Product Attribute | Attribute Value |
| HTS | 8542330001 |
| PPAP | Unknown |
| Type | SR-Type |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Surface Mount |
| Polarity | Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Tape and Reel |
| Pin Count | 16 |
| Set/Reset | No |
| Automotive | Yes |
| Latch Mode | Transparent |
| Output Type | 3-State |
| PCB changed | 16 |
| Part Status | Active |
| Logic Family | HEF4000 |
| Package Width | 4(Max) |
| Package Height | 1.45(Max) |
| Package Length | 10(Max) |
| Supplier Package | SO |
| Process Technology | CMOS |
| Number of Inputs per Chip | 8 |
| Number of Outputs per Chip | 4 |
| Supplier Temperature Grade | Industrial |
| Number of Channels per Chip | 4 |
| Number of Elements per Chip | 1 |
| Maximum Quiescent Current (uA) | 80 |
| Maximum Operating Temperature (°C) | 85 |
| Minimum Operating Temperature (°C) | -40 |
| Number of Input Enables per Element | 0 |
| Absolute Propagation Delay Time (ns) | 180 |
| Maximum Operating Supply Voltage (V) | 15 |
| Minimum Operating Supply Voltage (V) | 3 |
| Number of Output Enables per Element | 1 |
| Typical Operating Supply Voltage (V) | 3.3|5|9|12 |
| Maximum Low Level Output Current (mA) | 3.6(Min) |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -3.6 |
| Number of Selection Inputs per Element | 0 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 180@5V|70@10V|50@15V |
| Description |
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