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Latches SN74F573NE4
Texas Instruments
SN74F573NE4
--
Standard and Specialty Logic
Latches
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| Type | D-Type |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Through Hole |
| Polarity | Non-Inverting |
| Packaging | Tube |
| Pin Count | 20 |
| Set/Reset | No |
| Automotive | No |
| Latch Mode | Transparent |
| Lead Shape | Through Hole |
| Output Type | 3-State |
| PCB changed | 20 |
| Part Status | Unconfirmed |
| Logic Family | F |
| Package Width | 6.6(Max) |
| Package Height | 5.08(Max) - 0.51(Min) |
| Package Length | 26.92(Max) |
| Supplier Package | PDIP |
| Process Technology | Bipolar |
| Standard Package Name | DIP |
| Number of Inputs per Chip | 8 |
| Number of Outputs per Chip | 8 |
| Supplier Temperature Grade | Commercial |
| Number of Channels per Chip | 8 |
| Number of Elements per Chip | 1 |
| Maximum Operating Temperature (°C) | 70 |
| Minimum Operating Temperature (°C) | 0 |
| Number of Input Enables per Element | 1 |
| Absolute Propagation Delay Time (ns) | 13 |
| Maximum Operating Supply Voltage (V) | 5.5 |
| Minimum Operating Supply Voltage (V) | 4.5 |
| Number of Output Enables per Element | 1 |
| Typical Operating Supply Voltage (V) | 5 |
| Maximum Low Level Output Current (mA) | 24 |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -3 |
| Number of Selection Inputs per Element | 0 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 7@5V |
| Description |
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