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Latches SNJ54LVC373AW
Texas Instruments
SNJ54LVC373AW
--
Standard and Specialty Logic
Latches
Specification
| Product Attribute | Attribute Value |
| HTS | 8542330001 |
| PPAP | No |
| Type | D-Type |
| EU RoHS | Not Compliant |
| Bus Hold | No |
| Mounting | Surface Mount |
| Polarity | Non-Inverting |
| ECCN (US) | EAR99 |
| Packaging | Tube |
| Pin Count | 20 |
| Set/Reset | No |
| Automotive | No |
| Latch Mode | Transparent |
| Lead Shape | Flat |
| Output Type | 3-State |
| PCB changed | 20 |
| Part Status | Active |
| Logic Family | LVC |
| Package Width | 7.62(Max) |
| Package Height | 2.45(Max) |
| Package Length | 13.72(Max) |
| Supplier Package | CFPAK |
| Tolerant I/Os (V) | 5.5 Inputs |
| Process Technology | CMOS |
| Standard Package Name | FPAK |
| Number of Inputs per Chip | 8 |
| Number of Outputs per Chip | 8 |
| Supplier Temperature Grade | Military |
| Number of Channels per Chip | 8 |
| Number of Elements per Chip | 1 |
| Maximum Quiescent Current (uA) | 10 |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -55 |
| Number of Input Enables per Element | 1 |
| Absolute Propagation Delay Time (ns) | 9.5 |
| Maximum Operating Supply Voltage (V) | 3.6 |
| Minimum Operating Supply Voltage (V) | 2 |
| Number of Output Enables per Element | 1 |
| Typical Operating Supply Voltage (V) | 2.5|3.3 |
| Maximum Low Level Output Current (mA) | 24 |
| Propagation Delay Test Condition (pF) | 50 |
| Maximum High Level Output Current (mA) | -24 |
| Number of Selection Inputs per Element | 0 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 8.5@2.7V|7.5@3.3V |
| Description |
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