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Latches SY100E175JZ
Microchip Technology
SY100E175JZ
--
Standard and Specialty Logic
Latches
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| Type | D-Type |
| EU RoHS | Compliant |
| Bus Hold | No |
| Mounting | Surface Mount |
| Polarity | Non-Inverting |
| ECCN (US) | EAR99 |
| Pin Count | 28 |
| Set/Reset | Master Reset |
| Automotive | No |
| Latch Mode | Transparent |
| PCB changed | 28 |
| Part Status | Obsolete |
| Logic Family | ECL |
| Package Width | 11.48 |
| Package Height | 3.68(Min) |
| Package Length | 11.48 |
| Supplier Package | PLCC |
| Process Technology | ECL |
| Number of Inputs per Chip | 9 |
| Number of Outputs per Chip | 9 |
| Supplier Temperature Grade | Commercial |
| Number of Channels per Chip | 9 |
| Number of Elements per Chip | 1 |
| Maximum Operating Temperature (°C) | 85 |
| Minimum Operating Temperature (°C) | 0 |
| Number of Input Enables per Element | 1 |
| Absolute Propagation Delay Time (ns) | 1.45 |
| Maximum Operating Supply Voltage (V) | -4.2 |
| Minimum Operating Supply Voltage (V) | -5.5 |
| Number of Output Enables per Element | 0 |
| Typical Operating Supply Voltage (V) | -5 |
| Number of Selection Inputs per Element | 0 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 0.8@-4.2V to -5.5V |
| Description |
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