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Parity Generators and Checkers SNJ54LS280FK
Texas Instruments
SNJ54LS280FK
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Standard and Specialty Logic
Parity Generators and Checkers
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| EU RoHS | Not Compliant |
| Mounting | Surface Mount |
| ECCN (US) | 3A001.a.2.c |
| Packaging | Tube |
| Pin Count | 20 |
| Automotive | No |
| Lead Shape | No Lead |
| PCB changed | 20 |
| Part Status | Obsolete |
| Logic Family | LS |
| Package Width | 9.09(Max) |
| Logic Function | Parity Generator/Checker |
| Number of Bits | 9 |
| Package Height | 2.03(Max) |
| Package Length | 9.09(Max) |
| Supplier Package | CLLCC |
| Process Technology | Bipolar |
| Standard Package Name | LLCC |
| Supplier Temperature Grade | Military |
| Number of Elements per Chip | 1 |
| Maximum Power Dissipation (mW) | 80(Typ) |
| Maximum Quiescent Current (uA) | 16000(Typ) |
| Maximum Operating Temperature (°C) | 125 |
| Minimum Operating Temperature (°C) | -55 |
| Absolute Propagation Delay Time (ns) | 50 |
| Maximum Operating Supply Voltage (V) | 5.5 |
| Minimum Operating Supply Voltage (V) | 4.5 |
| Typical Operating Supply Voltage (V) | 5 |
| Maximum Low Level Output Current (mA) | 4 |
| Maximum High Level Output Current (mA) | -0.4 |
| Maximum Propagation Delay Time @ Maximum CL (ns) | 50@5V |
| Description |
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