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SRAM Chip K6X1008C2D-DF55000
Samsung Electronics
K6X1008C2D-DF55000
--
Memory
SRAM Chip
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| EU RoHS | Not Compliant |
| Mounting | Through Hole |
| ECCN (US) | EAR99 |
| Pin Count | 32 |
| Automotive | No |
| Lead Shape | Through Hole |
| PCB changed | 32 |
| Part Status | Obsolete |
| Timing Type | Asynchronous |
| Package Width | 13.6 |
| Package Height | 3.81 |
| Package Length | 42.31(Max) |
| Number of Ports | 1 |
| Number of Words | 128K |
| Supplier Package | PDIP |
| Chip Density (bit) | 1M |
| Process Technology | CMOS |
| Max. Access Time (ns) | 55 |
| Standard Package Name | DIP |
| Data Rate Architecture | SDR |
| Operating Current (mA) | 25 |
| Address Bus Width (bit) | 17 |
| Number of Bits/Word (bit) | 8 |
| Supplier Temperature Grade | Industrial |
| Maximum Operating Temperature (°C) | 85 |
| Minimum Operating Temperature (°C) | -40 |
| Maximum Operating Supply Voltage (V) | 5.5 |
| Minimum Operating Supply Voltage (V) | 4.5 |
| Typical Operating Supply Voltage (V) | 5 |
| Description |
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