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DRAM Chip K4B2G0846D-HCH9
Samsung Electronics
K4B2G0846D-HCH9
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Memory
DRAM Chip
Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| EU RoHS | Compliant |
| DRAM Type | DDR3 SDRAM |
| ECCN (US) | EAR99 |
| Automotive | No |
| Part Status | Obsolete |
| Organization | 256Mx8 |
| Interface Type | SSTL_1.5 |
| Chip Density (bit) | 2G |
| Data Bus Width (bit) | 8 |
| Operating Current (mA) | 80 |
| Address Bus Width (bit) | 18 |
| Maximum Access Time (ns) | 0.255 |
| Maximum Clock Rate (MHz) | 1333 |
| Number of Internal Banks | 8 |
| Number of Words per Bank | 32M |
| Number of Bits/Word (bit) | 8 |
| Number of I/O Lines (bit) | 8 |
| Maximum Operating Temperature (°C) | 95 |
| Minimum Operating Temperature (°C) | 0 |
| Maximum Operating Supply Voltage (V) | 1.575 |
| Minimum Operating Supply Voltage (V) | 1.425 |
| Typical Operating Supply Voltage (V) | 1.5 |
| Description |
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