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Specification
| Product Attribute | Attribute Value |
| PPAP | No |
| EU RoHS | Compliant |
| Material | Si |
| Mounting | Surface Mount |
| ECCN (US) | EAR99 |
| Packaging | Tape and Reel |
| Pin Count | 8 |
| Automotive | No |
| Lead Shape | No Lead |
| PCB changed | 8 |
| Part Status | Obsolete |
| Channel Mode | Enhancement |
| Channel Type | N |
| Configuration | Dual |
| Package Width | 6 |
| Package Height | 0.5 |
| Package Length | 5 |
| Product Category | Power MOSFET |
| Supplier Package | DFN EP |
| Maximum IDSS (uA) | 1@Q 1|500@Q 2 |
| Process Technology | PowerTrench |
| Standard Package Name | DFN |
| Typical Fall Time (ns) | 2.3@Q 1|5.2@Q 2 |
| Typical Rise Time (ns) | 2.5@Q 1|7.6@Q 2 |
| Number of Elements per Chip | 2 |
| Maximum Power Dissipation (mW) | 2200@Q 1|2500@Q 2 |
| Typical Gate Charge @ 10V (nC) | 20@Q 1|81@Q 2 |
| Typical Gate Charge @ Vgs (nC) | 20@10V|9.3@4.5V@Q 1|81@10V|37@4.5V@Q 2 |
| Maximum Gate Source Voltage (V) | ±20 |
| Typical Output Capacitance (pF) | 445@Q 1|2150@Q 2 |
| Typical Turn-On Delay Time (ns) | 8.6@Q 1|18@Q 2 |
| Maximum Drain Source Voltage (V) | 30 |
| Typical Gate Plateau Voltage (V) | 2.7@Q 2|3.5@Q 1 |
| Typical Turn-Off Delay Time (ns) | 20@Q 1|45@Q 2 |
| Maximum Diode Forward Voltage (V) | 1.2 |
| Typical Diode Forward Voltage (V) | 0.7@Q 2|0.8@Q 1 |
| Typical Gate to Drain Charge (nC) | 2.2@Q 1|9.6@Q 2 |
| Maximum Gate Threshold Voltage (V) | 3 |
| Minimum Gate Threshold Voltage (V) | 1 |
| Typical Gate Threshold Voltage (V) | 1.8@Q 1|1.5@Q 2 |
| Typical Gate to Source Charge (nC) | 4.3@Q 1|13@Q 2 |
| Typical Reverse Recovery Time (ns) | 27@Q 1|47@Q 2 |
| Maximum Operating Temperature (°C) | 150 |
| Minimum Operating Temperature (°C) | -55 |
| Maximum Continuous Drain Current (A) | 12@Q 1|22@Q 2 |
| Operating Junction Temperature (°C) | -55 to 150 |
| Typical Input Capacitance @ Vds (pF) | 1315@15V@Q 1|5265@15V@Q 2 |
| Typical Reverse Recovery Charge (nC) | 10@Q 1|80@Q 2 |
| Maximum Drain Source Resistance (mOhm) | 7.5@10V@Q 1|2.8@10V@Q 2 |
| Maximum Gate Source Leakage Current (nA) | 100 |
| Maximum Positive Gate Source Voltage (V) | 20 |
| Maximum Pulsed Drain Current @ TC=25°C (A) | 40@Q 1|60@Q 2 |
| Maximum Power Dissipation on PCB @ TC=25°C (W) | 2.2@Q 1|2.5@Q 2 |
| Typical Reverse Transfer Capacitance @ Vds (pF) | 45@15V@Q 1|200@15V@Q 2 |
| Maximum Continuous Drain Current on PCB @ TC=25°C (A) | 12@Q 1|22@Q 2 |
| Maximum Junction Ambient Thermal Resistance on PCB (°C/W) | 125@Q 1|120@Q 2 |
| Description |
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